The expanding availability of application specific integrated circuit (ASIC) technology to signal processing system manufacturers, particularly those who design and produce systems for sophisticated applications such as spaceborne communication and defense systems, has resulted in the use of an increasing number of gate array, standard cell, and silicon compiler-based chips in complex and hostile environment programs. Some of these programs, especially those associated with space and military applications, require semiconductor chips that are hardened against single event upsets (SEU). This hardening applies to processor, random logic, and memory chips, thereby necessitating SEU immune latches and flip flops, as well as memory cells.
One previous proposal to prevent SEU in memory cells, described in an article by S. E. Diehl et al, entitled "Error Analysis and Prevention of Cosmic Ion-Induced Soft Errors in Static CMOS RAMs," IEEE Trans. Nuclear Science, Vol. NS-29, p 2032, December 1982, has been to employ special processing techniques, such as those which incorporate high sheet resistance cross-coupled poly resistors as part of the circuit architecture. To understand the effect of resistors on SEU, consider the unstabilized, cross-coupled CMOS inverter pair, diagrammatically illustrated at 11, 13 in FIG. 1, the inverter pair serving as the storage element in a memory. Sensitive areas of the memory are the drain regions of the complementary devices (the reverse biased junctions of "off" devices).
When an ion passes through silicon, it produces a track of electron-hole pairs. If the ion passes through a sensitive region, the electron-hole pairs along the track will be separated by the field of the reverse biased junction, resulting in an immediate current response that deposits charge on the node. This drift-current-driven, charge collection process can be enhanced by diffusion and the field funnelling effect, as described in articles by C. M. Hsiech et al, entitled "A Field-Funneling Effect on the Collection of Alpha Particle-Generated Carriers in Silicon Devices," IEEE Electron Device Letters, Vol. EDL-2 No. 4, p. 103, April 1982, and by C. Hu, entitled "Alpha Particle-Induced and Enhanced Collection of Carriers," IEEE Electron Device Letters, Vol. EDL-3 No. 2, p. 31, February 1982.
In the memory circuit of FIG. 1, consider the case of an ion hitting the reverse biased drain 21D of P-type transistor 21 of a CMOS inverter 11, the input and output nodes of which are cross-coupled with those of a CMOS inverter 13. Such a "hit" creates a current pulse (diagrammatically illustrated as a current source I1) which pulls output node 15 of inverter 11 high to very near Vdd. When this happens, two things can occur. First, after the current at node 15 subsides, the voltage on the node can recover to its original value. The time required for node 15 to recover is referred to as the recovery time tR. It should be noted that the recovery time tR depends on the charge deposited (length and amplitude of the current pulse) and the current drive capability of N-type transistor 22 of CMOS inverter pair 11, to which the drain of P-type transistor 21 is connected. Secondly, when the voltage at node 15 is pulled high, node 16 of the other CMOS inverter 13 can begin to fall, thereby providing the feedback for upset.
In summary, a hit at the drain 21D of transistor 21 causes nodes 15 and 16 to be at the same voltage level (V.sub.DD) for a short period of time. Upset will not occur if the recovery time tR is less than the inverter falling propagation delay tdf (tR&lt;tdf). A similar analysis can be conducted for the case of a "hit" at the off drain 32D of N-type transistor 32, to which the drain of P-type transistor 31 of inverter pair 1 is connected.
By inserting resistors in the feedback paths of the inverter pairs, as diagrammatically illustrated at 41, 42 in FIG. 2, the value of falling propagation delay tdf is increased, so that it is always greater than tR. In a sense, resistors 41, 42 degrade the inherent regenerative feedback mechanism, thereby decoupling storage nodes 15, 16 from one another. This technique has proven effective in eliminating SEU and is used extensively throughout industry. However, the technique is not without its drawbacks. Extra processing steps are required to fabricate the resistors which increases turn time and cost. The resistors are implemented with lightly doped polysilicon and therefore have a large negative temperature coefficient. In order to insure SEU immunity at higher temperatures, very large room temperature resistors are required. Such large resistors substantially increase write times.
In a static random access memory (SRAM), the read operation is accomplished differentially, so that the resistors do not affect read times. The resistor hardening approach is most applicable to those systems requiring fast read times, but in which the write time is not critical. The value of resistance for SEU immunity is usually between 100K-1M requiring very lightly doped polysilicon. Process control of resistors implemented with lightly doped polysilicon is a considerable problem since the resistivity of lightly doped poly varies dramatically with small changes in doping.
The resistor hardening approach to stabilize latches and flip flops is described in an article by S. E. Diehl et al entitled "Considerations for Single Event Immune VLSI Logic," IEEE Trans. Nuclear Science, Vol. NS-30, p. 4501, December 1983, and FIG. 3 shows an example of a conventional CMOS clocked latch 51 comprising cross-coupled CMOS inverter pairs 11-13 stabilized with cross-coupling resistors 61, 63. A clocked complementary CMOS transistor pair 34 is coupled in circuit with inverter 13 and a clocked complementary CMOS transistor pair 36 is coupled in circuit with in input inverter 18 to which an input data terminal D is supplied. The Q output of the latch is derived from an output inverter 19.
Unfortunately, not only does the latch of FIG. 3, that has been stabilized with resistors, suffer from the same problems as the memory cell illustrated in FIG. 2, but, in addition, its write time is significantly increased. In the case of a latch or a flip-flop, long write times are unacceptable. In a synchronous environment, since the signal applied to the latch or flip-flop will be a clock signal, the time required to write into the latch will, in part, establish the clock frequency of the clocking regime. Substantial clock speed degradation due to resistor stabilization is unacceptable in high speed applications.
Because of the above drawbacks of the resistor stabilization approach, considerable attention has recently been focussed on silicon-on-insulator (SOI) technology as a means of reducing SEU susceptibility. Most radiation-hardened CMOS ASIC foundries are bulk processes. Implementation of either of the above-described solutions would result in one or more of the following: increased process complexity, reduced turn time, lower yield, higher cost and/or reduced performance. An SEU immune latch that could be implemented in any CMOS process without requiring technology, process or ground rule changes, and that possesses similar performance to a standard latch, would therefore be highly desirable for ASIC applications.
SOI offers inherent SEU resistance, no possibility of latchup and gamma dot upset/survivability levels that are 5-10.times. those of bulk. The inherent SEU resistance of SOI comes from the reduction in the charge collection depth of a potential ion strike. However, the reduction in charge collection depth often does not increase SEU resistance sufficiently to meet bit error rate (BER) requirements of high speed signalling applications. Other techniques such as custom layout to reduce strike areas, the addition of capacitors on sensitive nodes to increase the critical charge for upset, or the use of poly resistors in feedback paths must also be utilized. Thus, along with its merits, SOI also has some potential drawbacks.
For a number of reasons SOI yields are lower than those of similar bulk technologies. Also, very thin epitaxial layers are required to obtain the SEU immunity levels required by today's strategic systems. Obtaining high quality, thin epi-on-insulator has proven difficult, causing SOI starting wafers to be much more expensive than bulk wafers. These two factors make the cost of SOI parts much higher than bulk. SOI devices can also potentially have back-channel leakage problems and therefore may not provide as good a total dose hardness as an equivalent bulk technology. For applications requiring total dose and SEU hardness but not gamma dot, and in which recurring cost is a concern, SEU-hardened bulk technology may provide a viable alternative to SOI.